Vhdl Code For Serial Adder Using Finite State Machine

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California State University We study parallel adder circuits: Ripple-carry adder Carry-look ahead adder These adders are fast but expensive If speed is not critical, a more area-efficient scheme is to add the bits a pair at a time; which is called serial adder Serial Adder Using FSM. Serial Adder. If speed is not of great importance, a cost-effective option is to use a serial adder. Serial adder: bits are added a pair at a time (in one clock cycle). A=a n-1 a n-2 a 0, B=b n-1 b n-2 b 0. A finite-state machine (FSM) is a mechanism whose output is dependent not only on the current state of the input, but also on past input and output values. Whenever you need to create some sort of time-dependent algorithm in VHDL, or if you are faced with the problem of implementing a computer program in an FPGA, it can usually be solved. A finite-state machine (FSM) or simply a state machine is used to design both computer programs and sequential logic circuits. It is conceived as an abstract machine that can be in one of a finite number of user-defined states. The machine is in only one state at a time; the state it is in at any given time is called the current state. Moore State Machine. The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge. Let’s construct the sequence detector for the sequence 101 using both mealy state machine and moore state machine. Moore state require to four states st0,st1,st2,st3 to detect the 101 sequence.

This tutorial is about implementing a finite state machine is vhdl. I will go through each and every step of designing a finite state machine and simulating it. Xilinx is used as a tool to construct finite state machine and for simulation and testing purpose. I suppose you know what is finite state machine and why it is used? I will give a short introduction of finite state machines and then move on to the designing phase.
Finite state machine is a graphical model/representation of sequential activities or events. After representing and modeling the events they can be implemented easily in case of sequential logic designs.
Finite state machines can be utilized in many fields of study e.g neural networks, artificial intelligence, mathematics, games, robotics and sequential flow of data. Since we are dealing with the sequential circuits so i will explain their use in sequential circuit design in this tutorial.
There are many fsm(finite state machines) in existence. The two most popular used in digital combinational and sequential circuits are
  • Melay Machine
  • Moore Machine
The main difference between melay and moore is the computation of the next state. In melay machine the output depends on the current state and the input variables. Where as in moore machine the output depends on the current state only. There are also other differences which are hardly highlighted any where.
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Moore Machine Vhdl Code For Serial Adder Using Finite State Machine
  1. More number of states in moore compared to melay for same fsm.
  2. States changes after 1 clock cycle. Latency = 1.
  3. Synchronous output. Because the states are determined in a process.
  4. States are output.

Serial Adder Verilog

Mealy Machine

Vhdl Code For Serial Adder Using Finite State Machines

  1. Less number of states in mealy compared to moore for same fsm.
  2. State transition on the same clock cycle. Latency = 0.
  3. Asynchronous output.
  4. Transition are output.
In the below figure you can see a melay machine fsm. Fsm has four states S0, S1, S2 and S3. Outputs can be seen on the edges. Inputs are also on the edges. Transitions from one state to another take place on the bases of current state and the inputs. Fsm below is actually a counter. When input is 1 the state moves to next and when the input is 0 state jumps to previous. Counter is 4-bit but only one bit is manipulated in the counter. ‘1’ in the 4-bit output moves forward or backward depending on the state and input.

Vhdl Code For Serial Adder Using Finite State Machine Design

The top level entity of melay machine fsm is below. Output is 4-bit named count. Clock and reset are necessary signals for finite state machine. UpDw is a single bit input. When UpDw is 1 state jumps from current to next and when 0 it scroll back to previous state.

Vhdl Code For Serial Adder Using Finite State Machine Learning

Vhdl code for serial adder using finite state machine programmingVhdl Code For Serial Adder Using Finite State MachineState
Melay machine fsm counter – vhdl top level entity
Output of the melay machine can be seen in the figure below. If you match the behavior of the simulation with the actual state machine above you will find the behavior of the two similar. Which means that the finite state machine is implemented correctly. The simulation below is run on ISim simulator by xilinx.
Filed Under: Microcontroller Projects, VHDL

Serial Adder Circuit